UART参考设计 Xilinx提供VHDL代码
This zip file contains the following folders: \vhdl_source -- Source VHDL files: uart.vhd - top level file txmit.vhd - transmit portion of uart rcvr.vhd - - receive portion of uart \vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they do not instantiate the DUT. This can easily be done in a top-level VHDL file or a schematic. This folder contains the following files: txmit_tb.vhd -- Test bench for txmit.vhd. rcvr_tf.vhd -- Test bench for rcvr.vhd.
用户评论
recording1322 2018-12-08 15:19:54
不是很好用,参考价值一般
linzidong 2018-12-08 15:19:54
很简练,但是读不太懂,可以尝试用一用
qqfraud12564 2018-12-08 15:19:54
程序很好 加上buffer之后效果不错 虽然没有连到板子上试。。。