飞思卡尔的DDR3 pcb布局布线要求

The design guidelines presented in this application note apply to products that leverage the DDR3 SDRAM IP core, and they are based on a compilation of internal platforms designed by Freescale Semiconductor, Inc. The purpose of these guidelines is to minimize board-related issues across multiple memory topologies while allowing maxi mum flexibility for the board designer mum flexibility for the board designer