基于FPGA的usb1.1协议IP core设计
采用verilog编写,这里是USB核心的分层视图:usb1_core | +-usb_phy || |+-usb_tx_phy || |+-usb_rx_phy | +-usb1_utmi_if | +-usb1_pl || |+-usb1_pd || |+-usb1_pa || |+-usb1_idma || |+-usb1_pe | +-usb1_ctrl | +-
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