ARM硬件实验指导

ARM实验 仅供参考;//===================================================================== ;// File Name : 2410slib.s ;// Function : S3C2410 (Assembly) ;// Program : Shin, On Pil (SOP) ;// Date : March 20, 2002 ;// Version : 0.0 ;// History ;// 0.0 : Programming start (February 26,2002) -> SOP ;//===================================================================== ;//Interrupt, FIQ/IRQ disable NOINT EQU 0xc0 ;//1100 0000 ;//Check if tasm.exe(armasm -16 ...@ADS 1.0) is used. GBLL THUMBCODE [ {CONFIG} = 16 THUMBCODE SETL {TRUE} CODE32 | THUMBCODE SETL {FALSE} ] MACRO MOV_PC_LR [ THUMBCODE bx lr | mov pc,lr ] MEND AREA |C$$code|, CODE, READONLY ;//============== ;// CPSR I,F bit ;//============== ;//int SET_IF(void); ;//The return value is current CPSR. EXPORT SET_IF SET_IF ;//This function works only if the processor is in previliged mode. mrs r0,cpsr mov r1,r0 orr r1,r1,#NOINT msr cpsr_cxsf,r1 MOV_PC_LR ;//void WR_IF(int cpsrValue); EXPORT WR_IF WR_IF ;//This function works only if the processor is in previliged mode. msr cpsr_cxsf,r0 MOV_PC_LR ;//void CLR_IF(void); EXPORT CLR_IF CLR_IF ;//This function works only if the processor is in previliged mode. mrs r0,cpsr bic r0,r0,#NOINT msr cpsr_cxsf,r0 MOV_PC_LR ;//==================================== ;// MMU Cache/TLB/etc on/off functions ;//==================================== R1_I EQU (1