Multiply Your Sampling Rate with Time-Interleaved Data Converters

Abstract:Interleavingmultipleanalog-to-digitalconverters(ADCs)isusuallyperformedwiththeintenttoincreaseaconverterseffectivesamplerate,especiallyiftherearenooronlyfewoff-the-shelfADCsavailablethatfulfillthedesiredsample,linearityandACrequirementsofsuchapplications.However,time-interleavingdataconvertersisnotaneasytask,becauseevenwithperfectlylinearcomponents,gain/offsetmismatchesandtimingerrorscancauseundesiredspursintheoutputspectrum.Thefollowingarticleprovidesvaluableinsightintothetheoreticalapproachoftime-interleavedanalog-to-digitalconvertersandthekindofroadblocks(andhowtocompensateforthem)adesignerusuallyencounterswhenbuildingatime-interleavedsystem.Maxim>DesignSupport>TechnicalDocuments>Tutorials>A/DandD/AConversion/SamplingCircuits>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>Basestations/WirelessInfrastructure>APP989Maxim>DesignSupport>TechnicalDocuments>Tutorials>High-SpeedSignalProcessing>APP989Keywords:interleaving,time-interleaving,high-speed,analog-to-digitalconverter,high-speedADC,coarsequantizer,finequantizer,flashconverter,bandwidthlimitation,offseterror,gainerror,mismatches,nonlinearities,clockphasenoise,clockjitterMar01,2001TUTORIAL989MultiplyYourSamplingRatewithTime-InterleavedDataConvertersMar01,200