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Configuration and Readback of Virtex FPGAs Using JTAG BoundaryScan

TheIEEE1149.1TestAccessPort(TAP)andBoundary-Scanarchitecture,commonlyreferredtoasJTAG,isapopulartestingmethod.JTAGisanacronymfortheJointTestActionGroup,thetechnicalsubcommitteeinitiallyresponsiblefordevelopingthestandard.Thisstandardprovidesameansto

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358.93KB

2020-02-07 12:20

Routability and Fault Tolerance of FPGA Interconnect Architectures

ThispaperpresentsanewapproachfortheevaluationofFPGAroutingresourcesinthepresenceofinterconnectfaults.Allpossibleinterconnectfaultsforprogrammableswitchesandwiringchannelsareconsidered.Signalroutinginthepresenceoffaultyinterconnectresourcesisanalyzedatboth

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260.96KB

2019-09-05 07:33

System Level Self_Healing

System Level Self-Healing for Parametric Yield and Reliability Improvement under Power Bound

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544.99KB

2018-12-20 06:47

A Survey of Fault Tolerant Methodologies for FPGAs

A wide range of fault tolerance methods for FPGAs have been proposed. Approaches range from simple architectural redundancy to fully on-line adaptive implementations. The applications of these methods also differ; some are used only for manufacturing yield enhancement, while oth-ers can be used in-system. This survey attempts to provide an overview of the current state of the art for fault tolerance in FPGAs. It is assumed that faults have been previously detected and diagnosed; the methods presented are targeted towards tol erating the faults. A detailed descrip-tion of each method is presented. Where applicable, the methods are compared using common metrics. Results are summarized to present a succinct, comprehensive comparison of the different approaches.

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897KB

2018-12-07 14:12