sparten 6 数据手册 官方资料

sparten 6 数据手册 官方资料L XILINXLogiCoRE IP Spartan-6 FPGA Integrated Endpoint Block v1. 4 for PCI ExpressFunctional DescriptionFor information about the internal architecture of the Spartan-6 FPGA Endpoint block, seeUG654, Spartan-6 FPGA Integrated Endpoint block for PCI Express User Guide. Figure 1 illustrates theinterfaces to the coreSystem(sYS)interface·2CI上 xpress( PCIEX) interfaceConfiguration(CFGinterfaceTransaction(TRN) interfaceLogICORE IP Spartan-6 FPGAIntegrated Endpoint Block for PCI ExpressUser/TransactionPCILogic(TRN)PCI Express(PCI_EXP)ExpressSpartan-6 FPGATransceiverFabricIntegrated EndpointBlock forPCI Express(PCIE_ A1)ConfiguratinterfaceClock(s丫S)andResetFigure 1: Integrated Endpoint Block for PcI Express Top-level Functional Blocks and InterfacesProtocol LayersThe Integrated Endpoint Block follows the PCI Express Base Specification layering model, which consistsof the Physical, Data Link, and Transaction Layers. The protocol uses packets to exchange informationbetween layers. Packets are formed in the Transaction and Data Link Layers to carry information fromthe transmitting component to the receiving component Necessary information is added to the packetbeing transmitted which is required to handle the packet at specific layersAt the receiving end, each layer of the receiving element processes the incoming packet, strips the rel-evant information and forwards the packet to the next layer. As a result, the received packets are trans-formed from their Physical Layer representation to their Data Link Layer representation andTransaction Layer representationThe functions of the protocol layers includeGenerating and processing of TLPsFlow-control managementInitialization and power management functionsData protectionError checking and retry functionsPhysical link interface initializationDS718 September 21, 2010Www.xilinx.comProduct SpecificationLogicoRE IP Spartan-6 FPGA Integrated Endpoint Block v1.4 for PCI Express&X XILINXMaintenance and status trackingSerialization, de-serialization and other circuitry for interface operationEach of the protocol layers are defined in the sections that followPhysical LayerThe Physical layer exchanges information with the data link layer in an implementation-specific format. This layer is responsible for converting information received from the data link layer into anappropriate serialized format and transmitting it across the PCI Express Link at a frequency and widthcompatible with the remote deviceData Link LayerThe Data Link Layer acts as an intermediate stage between the Transaction Layer and the PhysicalLayer. Its primary responsibility is to provide a reliable mechanism for the exchange of TransactionLayer Packets(TLps) between the two Components on a LinkServices provided by the data Link layer include data exchange(tlps), error detection and recoveryinitialization services and the generation and consumption of Data Link layer Packets(DLLPs) DLLPsare the mechanism used to transfer information between data Link lavers of two directly connectedcomponents on the link. dLPs are used for conveying information such as Flow Control and TLPknow ledgmentsTransaction LayerThe upper layer of the PCI Express architecture is the Transaction Layer. The primary function of theTransaction Layer is the assembly and disassembly of Transaction Layer Packets(TLPs). Packets areformed in the transaction and data link layers to carry the information from the transmitting compo-nent to the receiving component. TLPs are used to communicate transactions, such as read and writeas well as certain types of events. To maximize the efficiency of communication between devices, theTransaction Layer implements a pipelined, full split-transaction protocol and manages credit-basedflow control of tlPsConfiguration ManagementThe Configuration Management Layer supports generation and reception of System ManagementMessages by communicating with the other layers and the user application. This layer contains thedevice configuration space and other system functions. The Configuration layer implements PCI/PCIExpress power management capabilities, and facilitates exchange of power management messages,including support for PME event generation Also implemented are user-triggered error message gen-eration, and user-read access to the device configuration spaceSupportXilinx provides technical support for this logiCoRE IP product when used as described in the productdocumentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented indevices that are not defined in the documentation, if customized beyond that allowed in the productdocumentation, or if changes are made to any section of the design labeled DO NOT MODIFYOrdering InformationThe Spartan-6 FPGA Integrated Block for PCI Express is included with the ISE CORE GeneratorTMwww.xilinx.comDS718 September 21, 2010Product SpecificationL XILINXLogiCoRE IP Spartan-6 FPGA Integrated Endpoint Block v1. 4 for PCI ExpressRevision HistoryThe following table shows the revision history for this documentDateVersionRevision06/2409nitial xilinⅹ draft.09/16/092.0Updated core to v1.2 and IsE to v11.3. Added support for VHDL12/02/092.5Updated to support ISE V11.404/19/103.0Updated core to v1.3 and ise to v12. 1. Removed licensing information(alicense is no longer required)09/21/104.0Updated core to v1. 4 and Ise to v12.3Notice of disclaimerXilinx is providing this design, code or information(collectively the "Information")to you"AS-Is" with nowarranty of any kind, express or implied. Xilinx makes no representation that the Information, or any particularimplementation thereof, is free from any claims of infringement. You are responsible for obtaining any rights youmay require for any implementation based on the Information. All specifications are subject to change withoutnotice. XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THEADEQUACY OF THE INFORMATION OR ANY IMPLEMENTATION BASED THEREON, INCLUDING BUTNOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREEFROM CLAIMS OF INFRINGEMENT AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY ORFITNESS FOR A PARTICULAR PURPOSE Except as stated herein, none of the Information may be copied,reproduced, distributed, republished, downloaded, displayed posted or transmitted in any form or by any meansincluding, but not limited to, electronic, mechanical, photocopying, recording or otherwise, without the priorwritten consent of xilinDS718 September 21, 2010Www.xilinx.comProduct Specification